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Cavium Multicore processor is based on the MIPS architecture. So while working on the card, I studied about the MIPS architecture and here are some to the basic architecture details about MIPS.

There were some of the questions in mind when I started reading about MIPS. viz..

• How MIPS architecture is superior to other architectures .
• How processor implements MIPS architecgure.
• What are the neccessary condition of MIPS.
• How MIPS lead to performance benefits.

After going through the article chain on MIPS, I hope you will be able to answer these(above) question.

MIPS Architecutre : The MIPS architecture incorporates powerful new instructions speifically for embedded application as well as proven memory management and priviledged mode control mechanism.

The MIPS-64 architecture is based on fixed length, regularly encoded instruction set, and it uses a load-store data model. It is streamlined to support optimized execution of high-levl languages. Arithmetic and logic operations uses a three operand format, allowing compilers to optimize complex expression formulation. Availability of 32 general-purpose registers enables compilers to further optimize code generation by keeping frequently accessed data in the registers.

Flexibility of high performance caches and memory management schemes continues to be a strenght of the MIPS architecture.

The addition of data streaming and predicted operations supports the increasing computation needs of the MIPS architecture.

Fixed point DSP-type instructions further enhance multimedia processing. These instructions that include Multiply (MUL), Multiply and Add(MADD), Multiply And Subtract(MSUB) and “count loading 0s and 1s”, provide greater performace in processing data streams such as audio, video, and multimedia without adding additional DSP hardware to the system

Pipeline Architecute : MIPS processors all ue some variation of a pipleline in their architecute. A pipeline is divided into following descrete parts or statges:

• fetch
• arithmetic operation
• Memory Access
• Write Back

Types of pipeline:

• Normal
• Parallel
• Super Pipeline
• Superscalar pipeline

Load And Store Architecture : Generally it takes longer to perform operations in memory than it does to perform them in on-chip register. TO eliminate the longer access time or latency of in-memory operations, MIPS processor use load/store design. The processor has many registers on chip, and all operations are performed on operands held in these processor registers. Main memory is accessed only thrrough load/store instructions. This has many benefits

1. reducing the number of memory accesses, easing memory bandwidth requirements.
2. simplifying the instruction set.
3. making it easier for compilers toi optmize register allocation.

Originally Posted On: 2010-08-29 03:14:41

Anshul Makkar, anshul_makkar@justkernel.com

Tags: MIPS architecture